1. Field of the Invention
The present invention relates to a test facilitating circuit for easily carrying out a built-in test on a microprocessor, and particularly, to a test facilitating circuit that uses a cache memory incorporated in a microprocessor as well as an inexpensive tester, to efficiently test the microprocessor.
2. Description of the Prior Art
FIG. 8 shows a microprocessor having a cache memory, according to a prior art. A built-in test is carried out on the microprocessor.
The microprocessor 800 has a cache memory 1 made of an instruction cache and a data cache, a decoder 2 for decoding an instruction to execute, an address translation unit 3 such as a translation look-aside buffer (TLB) for translating a logical address into a physical address, an operation unit 4 such as an integer data path, ALU, or RF and a floating point unit 5 for executing the instruction decoded by the decoder 2, a sequence control unit 6 such as a branch unit or a branch buffer for controlling the sequence of execution of instructions, a program counter 7, a selector 8 for selecting one of the addresses provided by the sequence control unit 6 and program counter 7, a cache control unit 9 for controlling an access to the cache memory 1 based on the address selected by the selector 8, and an external interface 10 for interfacing data transmission between the outside and the cache memory 1.
The microprocessor 800 has a test mode to test the cache memory 1 by directly writing and reading data to and from the cache memory 1 from the outside. The test mode is used to select good ones among mass-produced microprocessors, and once the microprocessors are shipped, the test mode is not usually used. The test mode is also called the cache test mode in this specification.
The cache test mode externally provides addresses and data to directly access the cache memory 1 and tests whether or not the cache memory 1 has manufacturing defects. Input/output (I/O) pins for passing the addresses and data used for the cache test mode are multiplexed with other pins. The microprocessor 800 may automatically generate the necessary addresses for the cache test mode.
Dotted lines in FIG. 8 indicate address and data paths used in the cache test mode.
When a microprocessor is reset, an uncache/unmap operation is carried out. This operation fetches a first instruction from a specific address that is not in a cache memory and requires no address translation, to execute a boot-up sequence for setting up the microprocessor. The boot-up sequence invalidates the cache memory and initializes a translation look-aside buffer (TLB) used for address translation.
Thereafter, the microprocessor accesses an address in the cache memory 1 or a logical address to be translated into a physical address, to start executing OS (operating system) and application programs.
The microprocessor 800 of the prior art must receive a maximum frequency test before shipment. This test needs a tester that must have higher performance than the maximum performance of the microprocessor 800 to test. Accordingly, the tester is expensive. In addition, the tester must have as many channels as the number of pins of the microprocessor 800 when testing the functions of the microprocessor 800.
Conventional microprocessors have a special cache test mode to test an internal cache memory by directly writing and reading data to and from the cache memory. This mode is not used in a usual operation and is capable of testing the cache memory as if it is a simple memory.
Testers for testing the conventional microprocessors must have higher performance than the maximum performance of the microprocessors, which is improving day by day. Improving the performance of testers results in increasing testing costs.
Recent LSI chips have additional buses such as a bus for a secondary cache, to increase the number of pins of the chips. This results in increasing the number of tester channels that are expensive, thereby further increasing testing costs.
As mentioned above, the performance of microprocessors having an internal cache memory is improving in short periods, and testers for testing the microprocessors must improve their performance accordingly, thereby increasing testing costs.